Pseudo-random variable generators

have since a long time has been used for encryption key designing purpose in

cryptography. Having a strong undetectable encryption code is the primary and

critical component of any kind of security in the cyber space. We see stronger

and better encryptions every day and our Internet-laced world would be a far

riskier place if we didn’t. A stronger encryption would mean an unbreakable

encryption. Any weakness in the encryption will be exploited by hackers,

criminals or foreign governments. There are a few methods to bypass the

encryption which in technical terms is called a “backdoor”. This means if a

backdoor to a cryptographic key system exists it can be easily exploited for

leaking out confidential information. 1,2,3,4

Today with growing cases of

cyber-crimes, trespassing and hacking, various methods of increasing security

over the internet and other confidential areas have come up like Triple DES5,

Double Encryption2,3 and many other Secure Cryptographic storage designs2,3,4.

These all methods seem to have very complicated algorithms and tedious code

writing processes. Hence to through this paper we propose an easy but difficult

to decode method of enhancing the security of an encryption key using a

pseudo-random generator specifically, the Linear Feedback Shift Register with

modifications in its final output. In our method of generating the novel result

of the output of an LFSR we are using VHDL Behavioral modulation while designing

the code for the LFSR in the software. The target device that we have used is

Xilinx Spartan 3A and performed simulation and synthesis using Xilinx

ISE.6,7,8 The practical exhibition of our work can be done by burning the

VHDL program in either a FPGA or CPLD kit compatible with the Spartan 3A family9.

I.

Related work

Linear Feedback Shift

Register is a good candidate for generating random numbers because logical

circuit variation are high2,3,4,6 .We can easily modify the LFSR and produce

different forms of random numbers. So it provides good security for

transmission. And also the software and hardware implementation of LFSR is very

easy. A Linear Feedback Shift Register (LFSR) is a shift

register whose input bit is a linear function of its previous state. Feedback

around a LFSR’s shift register comes from a selection of points (taps) in the

register chain and constitutes X-ORing

or X-Noring these taps to provide tap(s) back into the register. 8,10

Register bits that do not need an input tap, operate as a standard shift

register. It is this feedback that causes the register to loop through

repetitive sequences of pseudo-random values. 11The choice of taps determines

how many values there are in a given sequence before the sequence repeats. From

8,10 we get to know that for a 5-bit LFSR, if tap number 1 and 4 are X-ored

or X-nored then the LFSR gives the maximum number of states of random variables

which is equal to 2n-1 states i.e. 31 states of random variables

will be generated before the sequence repeats. Also, a seed value is to be

given as the first input to the LFSR design. 11,12

Linear feedback shift registers as

maximal length sequence generators are widely used in stream ciphers for key

stream generation due to their good statistical properties, large period, low

implementation costs, and are readily analysed using algebraic techniques.6

In cryptography counter modes are

usually used to convert block ciphers into stream ciphers.6 But in our paper

we will be applying it to increase the complexity of the LFSR output.

VHDL (VHSIC Hardware Descriptive

Language) is a hardware descriptive language used in electronic design

automation to describe digital and mixed signal system such as integrated

circuits.13,14,15 Behavioral modelling of VHDL8,10 coding is usually

preferred for complex circuit designs like for the designing of our X-ORed LFSR

and Counter.

The below Figure 1 represents the

block diagram of a 5-bit LFSR, consisting of 5 D-Flip flops (D-FF) placed in

series, and providing an X-ored feedback of the outputs of 2nd and 5th

D-FF6. Output is taken from each flip flop with bits moving from LSB to MSB

flip flop in each clock pulse.

Figure 1: Block diagram for

a 5-bit maximum length LFSR

II.

PROPOSED ALGORITHM

A. Design Considerations and Assumptions:

·

The same Positive edge

triggered clock with a constant time period is being used for design of both

the LFSR and counter.

·

The LFSR and Counter are

designed using behavioral modeling

·

The LFSR will of 5 bits giving up to 31 states

(2n-1 ) and the counter being used is a 5-bit Synchronous Up counter.

·

For maximum length of random

sequence to be generated the output of D-Flip flop 1 and 4 will be considered

as taps (inputs to the X-nor gate).

Novel Random

Variable Sequence

Fig 3.5: Block Diagram of the

proposed Idea

B. Description of the Proposed Algorithm:

The aim of the proposed algorithm is to

transform the genuine LFSR producing repetitive sequences of pseudo-random into

a non-repetitive sequence generator. The proposed algorithm consists of 3 main

steps-

Step 1: Designing of the

Linear Feedback Shift Register:

As discussed above, A Linear Feedback Shift Register (LFSR) is a

shift register whose input bit is a linear function of its previous state. Thus

the coding will follow a loop pattern where the output keeps repeating after

every 2n-1th time(here being after 31st time or state).

PSEUDO CODE:

Statement 1– Declare Clock and Reset Inputs and outputs as those of

the LFSR from 0 to N-1.

Statement 2–Signal output of each D-ff to the input of the next

generating taps.

Statement 3–Initial seed value provided for maximum length

Statement 3–Feedback the X-ORed or X-NORed value of the first and

fourth tap if it’s a case of maximum length of output generation.

Statement 4–Let the loop continue for infinite duration. 7,8,10

Step 2: Designing of the

Counter:

A 5 bit synchronous counter will count from ‘00000’ up to its

maximum 5 bit state ‘11111’.

PSEUDOCODE:

Statement 1–Declaring clock as input and the 5bit output as 4 down

to 0.

Statement 2–Appling the looped logic of S=S+1 for every positive

edge triggering.

Step 3: Designing of the

X-ORed mechanism:

Such a code can be best understood if structural modeling is used to

design the mechanism as then each output bit of the LFSR and Counter can be

clearly portmaped with the other, hence preventing any confusion and errors.